INVITED TALKS
2nd Workshop on
Highly Parallel Processing on a Chip (HPPC
2008)
August 26, 2008, UAB-ULPGC, Las Palmas de
Gran Canaria, Spain
in conjunction with
August 26-29, 2008, UAB-ULPGC, Las Palmas
de Gran Canaria, Spain.
KEYNOTE 1
Models for Parallel and Hierarchical
On-Chip Computation
Gianfranco Bilardi, University of Padova,
Italy
Abstract: Chip
Multiprocessors have the potential to deliver significant
performance, easily in the Teraflop/s range within a few years.
To achieve a full exploitation of this potential, it is
crucial to develop adequate models of computation that can
guide the optimization of algorithms and of architectures.
This talk will present results and open issues along
three directions:
1. The pipeline of accesses in the memory
hierarchy to increase memory bandwidth utilization.
2. The network-oblivious approach as a step
toward efficient algorithmic portability across chip
multiprocessors with different organizations.
3. The information-exchange methodology to
identify the best partition of chip area between functional
units and storage elements, under chip I/O bandwidth
constraints.
Bio: Gianfranco
Bilardi is Professor of Computer Science at the University of
Padova, Italy. He also holds an Academic Visitor position
with IBM Research, at the T.J. Watson Laboratory.
Previously, he has been an Assistant Professor at Cornell
University, New York, USA. He has visited several other
institutions, including the University of
California at Berkeley and at Irvine, Brown
University, the University of Illinois at Chicago, and the Max
Planck Institut fur Informatik in Saarbrucken, Germany.
Bilardi's research is mostly in the areas
of parallel algorithms and architectures, high performance
computing, VLSI, and signal processing. This research has been
sponsored by various agencies and companies, both in Europe and
in the USA. He has coordinated a number of research
projects, at the national and at the European level. Currently,
he is the Coordinator of the Center of Excellence MIUR
"Science and Applications of Advanced Computing
Paradigms," established in 2001. and involving researchers
in different areas of informatics and computational sciences
and engineering. He has (co)authored over 75
international publications.
He is part of the executive committee of
the Bertinoro International Center for Informatics (BiCi),
which hosts and partially sponsors around twenty events per
year, between workshops, conferences, and schools. He has
served on many program committees of international conferences,
editorial boards, and research evaluation committees. With P.
Pattnaik, he has established and coordinated the workshop
series "ScalPerf: Scalable Approaches to High Performance
and High Productivity Computing", whose 6th edition is
planned for September 2008.
KEYNOTE 2
Building a concurrency and resource
allocation model into a processor's ISA
Chris Jesshope,
University of Amsterdam, The Netherlands
Abstract: We
are now facing the prospect of no increases in computer
system's performance unless we harness and efficiently exploit
the concurrency that comes from multiple cores on a chip. It
should be emphasised that the issues in exploiting concurrency
are scale invariant and relate to a few simple parameters and
issues. These are: the ratio of the throughput of computation
and communication (both local and global), which determines how
computation can be distributed and the cost of concurrency
creation compared to computation, which determines the grain
size of the computation. Finally we need virtual concurrency or
parallel slack and an efficient data-driven scheduling
mechanism, in order to tolerate the latency in any asynchronous
activity in the computation, such as access to remote data and
resource sharing. The concurrency model used must also be well
behaved, i.e. provides determinism of the values computed
(although not necessarily the time required to compute them)
and safe composition. Although these concurrency issues are
scale invariant it makes sense to implement them at the lowest
scale possible, i.e. at the level of machine instructions,
which have overheads measured in single cycles. In this way,
all levels of concurrency may be exploited, which is important
when dealing with legacy or constrained code. This talk will
explore work undertaken at the University of Amsterdam in
designing and evaluating micro-grids of micro-threaded
processors that meet these requirements. Moreover the
concurrency model developed in this work, SVP, is free of
deadlock free under composition and has built into its
implementations issues which are considered to be operating
system ones. Namely it builds in the abstraction of a place,
which capture resources and security both in using places and
in controlling the execution of concurrency at a place. As the
implementation of the concurrency model also manages mapping
and scheduling of concurrency it can truly be said that SVP is
an operating system kernel built into the ISA of the processor.
Bio: Chris
Jesshope is Professor of Computer Systems Engineering at the
University of Amsterdam and has held this post since 2004.
Prior to this, he has held posts in a number of universities
including a Readership at Southampton University and a Chair at
Surrey University, two of the top Electronic Engineering
schools in the UK. Professor Jesshope is a Chartered Engineer,
a Fellow of the BCS, a Member of the IEEE and a Member of the
IEEE Computer Society. His professional activities have
included membership on various funding agency committees in
both the UK and the Netherlands and the prestigious post of
Editor of the IEE Proceedings part E (Computers and Digital
techniques) over a 10 year period. He has been involved in
numerous program committees, is the Founding Chair of the
steering committee of the Microgrid International Workshop on
on-chip concurrency and was the founding chair of the steering
committee for the EuroPar International Conference. He has also
been general chair for nine international conferences and
workshops. Professor Jesshope has given in excess of 50 invited
papers or keynote presentations in his career, has written or
edited 17 major works, including the very successful book
Parallel Computers and published in excess of 160 refereed
papers. Most of this work has been in the field of parallel
computer architectures and concurrent programming.
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