PROGRAM
2nd Workshop on
Highly Parallel Processing on a Chip (HPPC
2008)
August 26, 2008, UAB-ULPGC, Las Palmas de
Gran Canaria, Spain
in conjunction with
August 26-29, 2008, UAB-ULPGC, Las Palmas
de Gran Canaria, Spain.
TUESDAY AUGUST 26, 2008
SESSION 1 - Paradigms and algorithms for
CMPs
09:30-09:35
Opening remarks - Jesper Träff
and Martti Forsell, NEC Europe, VTT
09:35-10:35
Keynote - Models for Parallel and Hierarchical On-Chip
Computation - Gianfranco Bilardi,
University of Padova
10:35-11:00
Optimized Pipelined Parallel Merge Sort on the Cell BE - Jörg Keller and Christoph Kessler,
FernUniversität in Hagen, University of Linköping
11:00-11:30 --
Break --
SESSION 2 - Programming and execution
environments
11:30-11:55
Towards an Intelligent Environment for Programming Multi-core
Computing Systems - Sabri Pllana,
Siegfried Benkner, Eduard Mehofer, Lasse Natvig, and Fatos
Xhafa, University of Vienna, NTNU, Universitat
Politécnica de Catalunya
11:55-12:20
Adaptive Read Validation in Time-Based Software Transactional
Memory - Ehsan Atoofian and Amirali
Baniasadi, University of Victoria
12:20-12:45
Compile-time and Run-time Issues in an Auto-parallelisation
system for the Cell BE Processor - Alastair
Donaldson, Paul Keir, and Anton Lokhmotov, Codeplay Software,
University of Glasgow, Imperial College London
12:45-13:10 A
unified runtime system for heterogeneous multicore
architectures - Cédric
Augonnet and Raymond Namyst, LaBRI - INRIA Bordeaux
13:10-14:30 --
Lunch --
SESSION 3 - Hardware perspectives to
future of on-chip computing
14:30-14:55
(When) Will CMPs hit the Power Wall? - Cor Meenderinck and Ben Juurlink, Delft University of
Technology
14:55-15:55
Keynote - Building a concurrency and resource allocation model
into a processor's ISA - Chris
Jesshope, University of Amsterdam
15:55-16:00
Closing remarks - Jesper Träff
and Martti Forsell, NEC Europe, VTT
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