Workshop on Highly Parallel Processing on a Chip (HPPC)

KEYNOTE 1

Uzi Vishkin, UMIACS, University of Maryland

Abstract: Serial computing has become largely irrelevant for growth in computing performance at around 2003. Having already concluded that to maintain past performance growth rates, general-purpose computing must be overhauled to incorporate parallel computing at all levels of a computer system--including the programming model—all processor vendors put forward many-core roadmaps. They all expect exponential increase in the number of cores over at least a decade. This welcome development is also a cause for apprehension. The whole world of computing is now facing the same general-purpose parallel computing challenge that eluded computer science for so many years and the clock is ticking. It is becoming common knowledge that if you want your program to run faster you will have to program for parallelism, but the vendors who set up the rules have not yet provided clear and effective means (e.g., programming models and languages) for doing that. How can application software vendors be expected to make a large investment in new software developments, when they know that in a few years they are likely to have a whole new set of options for getting much better performance?! Namely, we are already in a problematic transition stage that slows down performance growth, and may cause a recession if it lasts too long. Unfortunately, some industry leaders are already predicting that the transition period can last a full decade.

The PRAM-On-Chip project started at UMD in 1997 foreseeing this challenge and opportunity. Building on PRAM--a parallel algorithmic approach that has never been seriously challenged on ease of thinking, or wealth of its knowledge-base—a comprehensive and coherent platform for on-chip general-purpose parallel computing has been developed and prototyped. Optimize single-task completion time, the platform accounts for application programming (VHDL/Verilog, OpenGL, MATLAB, etc), parallel algorithms, parallel programming, compiling, architecture and deep-submicron implementation, as well as backward compatibility on serial code. The approach goes after any type of application parallelism regardless of its amount, regularity, or grain size. Some prototyping highlights include: an eXplicit Multi-Threaded (XMT) architecture, a new 64-processor, 75MHz XMT (FPGA-based) computer, 90nm ASIC tape-out of the key interconnection network component, a basic compiler, class tested programming methodology where students are taught only parallel algorithms and pick the rest on their own, and ~100X speedups on applications.

The talk will overview some future plans and will argue that the PRAM-On-Chip approach is a promising candidate for providing the processor-of-the-future. It will also posit that focusing on a small number of promising approaches, such as PRAM-On-Chip, and accelerate their incubation and testing stage, would be most beneficial both: (i) for the field as a whole, and (ii) for an individual researcher who is seeking improved impact.

Bio: Uzi Vishkin is a permanent member of the University of Maryland Institute for Advanced Computer Science (UMIACS) and a Professor of Electrical and Computer Engineering since 1988. He got his DSc in Computer Science from the Technion—Israel Institute of Technology and his MSc and BSc in Mathematics from the Hebrew University, Jerusalem, Israel. He was Professor of Computer Science at Tel Aviv University and the Technion, research faculty at the Courant Institute, NYU and a post-doc at IBM T.J Watson. He is Fellow of the ACM and an ISI-Thompson Highly-Cited Researcher.

KEYNOTE 2

Societies of Cores and their Computing Culture

Thomas Sterling, Louisiana State University

Abstract: The performance opportunities enabled through multi-core chips and the efficiency potential of heterogeneous ISA and structures is creating a climate for computer architecture, highly parallel processing chips, and HPC systems unprecedented for more than a decade. But with change comes the uncertainty from competition of alternatives. One thing is clear: all systems will be parallel systems and all chips will be highly parallel. If so, then, how will the parallelism be represented and controlled and what will be the roles and responsibilities for managing system wide parallelism? This presentation will address both the exciting opportunities and challenges of highly parallel processing cores on chips and describe one possible path for future parallel ISA cores, ParalleX, which may enable the synthesis of many cores into one single scalable system.

Bio: Dr. Thomas Sterling is a Professor of Computer Science at Louisiana State University, a Faculty Associate at California Institute of Technology, and a Distinguished Visiting Scientist at Oak Ridge National Laboratory. He received his PhD as a Hertz Fellow from MIT in 1984. Dr. Sterling is probably best known as the “father” of Beowulf clusters and for his research on Petaflops computing architecture. He was one of several researchers to receive the Gordon Bell Prize for this work on Beowulf 1997. In 1996, he started the inter-disciplinary HTMT project to conduct a detailed point design study of an innovative Petaflops architecture. He currently leads the MIND memory accelerator architecture project for scalable data-intensive computing and is an investigator on the DOE sponsored Fast-OS Project to develop a new generation of configurable light-weight parallel runtime software system. Thomas is co-author of five books and holds six patents.

Figures 1-3. Thomas Sterling really puts his soul into the HPPC’07 keynote. Photos courtesy of Christian Lengauer.