PROGRAM
Workshop on
Highly Parallel Processing on a Chip (HPPC)
August 28, 2007, IRISA, Rennes, France
in conjunction with
August 28-31, 2007, IRISA, Rennes, France.
TUESDAY AUGUST 28, 2007
SESSION 1 - Alternative computing
paradigms for CMPs
09:00-09:15
Opening notes - Jesper Träff
and Martti Forsell, NEC Europe, VTT
09:15-10:05 Keynote - Towards Realizing a PRAM-On-Chip
Vision - Uzi Vishkin, UMIACS, University of Maryland
10:05-10:30 An
asynchronous many-core dataflow processor for D3AS prototype - Lorenzo Verdoscia and Roberto Vaccaro, ICAR-CNR
Italy
10:30-11:00 --
Break --
SESSION 2 - Transactional memory and
caching solutions
11:00-11:25
Hardware Transactional Memory with Operating System Support - Sasa Tomic, Adrian Cristal, Osman Unsal, and
Mateo Valero, Barcelona Supercomputing Center, Universitat
Politécnica de Catalunya
11:25-11:50
Auto-parallelisation of Sieve C++ programs - Alastair Donaldson, Colin Riley, Anton Lokhmotov, and
Andrew Cook, Codeplay Software, University of Cambridge
11:50-12:15
Adaptive L2 Cache for Chip Multiprocessors - Domingo Benítez, Juan Carlos Moure, Dolores
Isabel Rexachs, and Emilio Luque, University of Las Palmas,
Universidad Autonoma de Barcelona
12:15-12:40
COMA Cache Hierarchy for Microgrids of Microthreaded Cores - Li Zhang and Chris Jesshope, University of
Amsterdam
12:40-14:00 --
Lunch --
SESSION 3 - Language support and CMP
future directions
14:00-14:25
Parallelization of Bulk Operations for STL Dictionaries - Leonor Frias, and Johannes Singler, Universitat
Politécnica de Catalunya, Universität Karlsruhe
14:25-15:15 Keynote - Societies of Cores and their
Computing Culture - Thomas Sterling, Louisiana State University
15:15-15:30
Closing notes - Jesper Träff
and Martti Forsell, NEC Europe, VTT
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