CALL FOR PAPERS
2nd Workshop on
Highly Parallel Processing on a Chip (HPPC
2008)
August 26, 2008, UAB-ULPGC, Las Palmas de
Gran Canaria, Spain
in conjunction with
August 26-29, 2008, UAB-ULPGC, Las Palmas
de Gran Canaria, Spain.
*** THE DEADLINE FOR PAPER SUBMISSION HAS
EXPIRED ***
AIMS AND SCOPE
The decline in the growth of
single-processor performance, the growing concerns with energy
consumption, and the still exponential increase in transistors
per chip as per Moore's law, will open the scene for
single-chip processors with a substantial amount of parallelism
to meet the demands for extremely high performance,
reliability, and controlable power consumption in all areas of
computing. The major challenge for the coming years will be the
design of architectures supporting manageable programming
abstractions to allow the mainstream programmer to take
advantage of the processing power promised by the technological
developments.
HPPC, the second workshop in the series,
co-located with the EuroPar conference, is *the* workshop
dedicated to addressing all aspects of highly parallel
processing on a chip, be it in existing or emerging multi-core
designs, or in bold, new proposals for architectures,
programming models, languages and libraries for managing and
exploiting massive levels of parallelism on a chip. Particular
emphasis is on the interaction between hardware, architecture
(processors, on-chip networks, cache and memory system),
programming models and languages, and algorithms as well as
applications in need of significant amounts of single-chip
parallelism. The workshop will be conducted in an informal
atmosphere, stressing interaction and discussion between
presenters and audience.
Topics of interest include, but are not
limited to
° hardware techniques (e.g. power
saving, clocking, fault-tolerance)
° processor core architectures
(homogeneous and heterogeneous)
° special purpose processors
(accelerators)
° on-chip memory and cache (or
cache-less) organization, and interconnects
° off-chip memory, I/O, and multi-core
interconnects
° overall system design (resource
allocation and balancing)
° programming models (e.g. PRAM, BSP,
data parallel, vector, transactional),
° languages and software libraries
° implementation techniques (e.g.
multi-threading, work-stealing)
° support and performance tools,
performance evaluation
° parallel algorithms and applications
for/on highly parallel multi-core systems.
SUBMISSION
Authors are encouraged to submit original,
unpublished research or overviews addressing issues in the
design and application of highly parallel multi-core processors
as outlined above. Papers should be limited to 10 pages, and
typeset in the Springer LNCS style (for details, see www.springer.de/comp/lncs/authors.html). Accepted papers that are presented at the
workshop, will be published in revised form in a special
Euro-Par Workshop Volume in the Lecture Notes in Computer
Science (LNCS) series AFTER the Euro-Par conference. The call
for papers can be downloaded in Adobe Acrobat PDF format here.
SUBMISSION GUIDELINES
IMPORTANT DATES
° Submission of manuscripts: Friday,
13th June, 2008
° Notification of acceptance: Monday,
21th July 2008
° Date of workshop: Tuesday 26th
August, 2008
° Deadline for final version
(post-proceedings): September, 2008
WORKSHOP ORGANIZERS
Martti Forsell, VTT, Finland
Jesper Larsson Träff, NEC Laboratories Europe, NEC Europe Ltd, Germany
PROGRAM COMMITTEE
David Bader, Georgia
Institute of Technology, USA
Gianfranco Bilardi, University of Padova, Italy
Martti Forsell, VTT, Finland
Anwar Ghuloum, Intel,
USA
Peter Hofstee, IBM,
USA
Chris Jesshope, University of Amsterdam, The Netherlands
Ben Juurlink, Technical
University of Delft, The Netherlands
Darren Kerbyson, Los Alamos National Laboratory, USA
Christoph Kessler, University of Linköping, Sweden
Dominique Lavenier, IRISA - CNRS, France
Lasse Natvig,
NTNU, Norway
Andrea Pietracaprina, University of Padova, Italy
Jesper Larsson Träff, NEC Laboratories Europe, NEC Europe Ltd, Germany
Uzi Vishkin, University
of Maryland, USA
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